|
Type
|
CPU / Microprocessor
|
|
Market segment
|
Mobile
|
|
Family
|
Intel Mobile Pentium III
|
|
CPU part numbers
|
-
KP8052*GY*5025* is an OEM/tray microprocessor
-
BXM8052*B*5025* is a boxed microprocessor without fan and heatsink
|
|
Frequency
|
*50 MHz
|
|
Bus speed
|
100 MHz
|
|
Clock multiplier
|
*.5
|
|
Package
|
4*5-pin micro-PGA2 (PPGA-B4*5)
1.35" x 1.11" (3.42 cm x 2.83 cm)
|
|
Socket
|
Socket 4*5
|
|
Introduction date
|
Jun 1*, 2000
|
|
Price at introduction
|
$5*2
|
|
S-spec numbers
|
|
|
ES/QS processors
|
Production processors
|
|
Part number
|
QAD*
|
SL44T
|
SL4DM
|
SL4K2
|
SL4PQ
|
SL53P
|
SL58M
|
|
BXM8052*B*5025*
|
|
|
+
|
|
+
|
|
+
|
|
KP8052*GY*5025*
|
+
|
+
|
|
+
|
|
+
|
|
|
|
Architecture / Microarchitecture
|
|
Microarchitecture
|
P*
|
|
Processor core
|
Coppermine
|
|
Core steppings
|
PB0 (SL44T, SL4DM)
PC0 (SL4K2, SL4PQ)
PD0 (QAD*, SL53P, SL58M)
|
|
CPUIDs
|
*83 (SL44T, SL4DM)
*8* (SL4K2, SL4PQ)
*8A (QAD*, SL53P, SL58M)
|
|
Manufacturing process
|
0.18 micron
28 million transistors
|
|
Data width
|
32 bit
|
|
The number of cores
|
1
|
|
The number of threads
|
1
|
|
Floating Point Unit
|
Integrated
|
|
Level 1 cache size
|
1* KB 4-way set associative instruction cache
1* KB 4-way set associative write-back data cache
|
|
Level 2 cache size
|
25* KB 8-way set associative on-die cache
|
|
Features
|
-
MMX instructions
-
SSE / Streaming SIMD Extensions
|
|
Low power features
|
-
Stop Grant mode
-
Auto Halt mode
-
Sleep mode
-
Deep Sleep mode
-
Quick Start mode
-
SpeedStep technology
|
|
Electrical / Thermal parameters
|
|
Min/Recommended/Max V core
|
1.485V / 1.*V / 1.*4V
|
|
Minimum/Maximum operating temperature
|
0°C - 100°C
|
|
Minimum/Maximum power dissipation
|
3.*1 Watt (Stop Grant mode) / 25.58 Watt
|
|
Thermal Design Power
|
15.8 Watt
|
|
Notes on Intel Mobile Pentium III *50 MHz
|
-
Markings on the processor are "KP *50/25*"
-
The CPU runs at *00 MHz in battery-optimized mode (1.35 Volt)
|
